Interconnect Delay and Area Estimation for Multiple-Pin Nets
نویسندگان
چکیده
This paper studies interconnect delay and area estimation for multiple-pin nets with consideration of interconnect optimizations, including optimal wire sizing (OWS), and simultaneous bu er insertion/sizing and wire sizing (BISWS), under two types of optimization objectives: one is to minimize delay to a single critical sink, and the other is to minimize the maximum delay to all critical sinks. Our estimation models are accurate, yet an order of ten thousand times faster when compared with running corresponding complex optimization algorithms directly. Therefore, they are expected to be very useful to guide the interconnect-centric synthesis and planning for deep submicron circuit designs.
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